2008-08-14 QEMU 
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7409: static int main_loop(void) 7410: { 7411: int ret, timeout; 7412: #ifdef CONFIG_PROFILER 7413: int64_t ti; 7414: #endif 7415: CPUState *env; 7416: 7417: cur_cpu = first_cpu; 7418: next_cpu = cur_cpu->next_cpu ?: first_cpu; 7419: for(;;) { 7420: if (vm_running) { 7421: 7422: for(;;) { 7423: /* get next cpu */ 7424: env = next_cpu; 7425: #ifdef CONFIG_PROFILER 7426: ti = profile_getclock(); 7427: #endif 7428: ret = cpu_exec(env); 7429: #ifdef CONFIG_PROFILER 7430: qemu_time += profile_getclock() - ti; 7431: #endif 7432: next_cpu = env->next_cpu ?: first_cpu; 7433: if (event_pending) { 7434: ret = EXCP_INTERRUPT; 7435: event_pending = 0; 7436: break; 7437: } 7438: if (ret == EXCP_HLT) { 7439: /* Give the next CPU a chance to run. */ 7440: cur_cpu = env; 7441: continue; 7442: } 7443: if (ret != EXCP_HALTED) 7444: break; 7445: /* all CPUs are halted ? */ 7446: if (env == cur_cpu) 7447: break; 7448: } 7449: cur_cpu = env; 7450: 7451: if (shutdown_requested) { 7452: ret = EXCP_INTERRUPT; 7453: break; 7454: } 7455: if (reset_requested) { 7456: reset_requested = 0; 7457: qemu_system_reset(); 7458: ret = EXCP_INTERRUPT; 7459: } 7460: if (powerdown_requested) { 7461: powerdown_requested = 0; 7462: qemu_system_powerdown(); 7463: ret = EXCP_INTERRUPT; 7464: } 7465: if (ret == EXCP_DEBUG) { 7466: vm_stop(EXCP_DEBUG); 7467: } 7468: /* If all cpus are halted then wait until the next IRQ */ 7469: /* XXX: use timeout computed from timers */ 7470: if (ret == EXCP_HALTED) 7471: timeout = 10; 7472: else 7473: timeout = 0; 7474: } else { 7475: timeout = 10; 7476: } 7477: #ifdef CONFIG_PROFILER 7478: ti = profile_getclock(); 7479: #endif 7480: main_loop_wait(timeout); 7481: #ifdef CONFIG_PROFILER 7482: dev_time += profile_getclock() - ti; 7483: #endif 7484: } 7485: cpu_disable_ticks(); 7486: return ret; 7487: }
cpu_exec()はこんな感じになっている↓
285 /* main execution loop */ 286 287 int cpu_exec(CPUState *env1) 288 { 289 #define DECLARE_HOST_REGS 1 290 #include "hostregs_helper.h" 291 #if defined(TARGET_SPARC) 292 #if defined(reg_REGWPTR) 293 uint32_t *saved_regwptr; 294 #endif 295 #endif 296 int ret, interrupt_request; 297 void (*gen_func)(void); 298 TranslationBlock *tb; 299 uint8_t *tc_ptr; 300 301 if (cpu_halted(env1) == EXCP_HALTED) 302 return EXCP_HALTED; 303 304 cpu_single_env = env1; 305 306 /* first we save global registers */ 307 #define SAVE_HOST_REGS 1 308 #include "hostregs_helper.h" 309 env = env1; 310 SAVE_GLOBALS(); 311 312 env_to_regs(); 313 #if defined(TARGET_I386) 314 /* put eflags in CPU temporary format */ 315 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 316 DF = 1 - (2 * ((env->eflags >> 10) & 1)); 317 CC_OP = CC_OP_EFLAGS; 318 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 319 #elif defined(TARGET_SPARC) 320 #if defined(reg_REGWPTR) 321 saved_regwptr = REGWPTR; 322 #endif 323 #elif defined(TARGET_M68K) 324 env->cc_op = CC_OP_FLAGS; 325 env->cc_dest = env->sr & 0xf; 326 env->cc_x = (env->sr >> 4) & 1; 327 #elif defined(TARGET_ALPHA) 328 #elif defined(TARGET_ARM) 329 #elif defined(TARGET_PPC) 330 #elif defined(TARGET_MIPS) 331 #elif defined(TARGET_SH4) 332 #elif defined(TARGET_CRIS) 333 /* XXXXX */ 334 #else 335 #error unsupported target CPU 336 #endif 337 env->exception_index = -1; 338 339 /* prepare setjmp context for exception handling */ 340 for(;;) { 341 if (setjmp(env->jmp_env) == 0) { 342 env->current_tb = NULL; 343 /* if an exception is pending, we execute it here */ 344 if (env->exception_index >= 0) { 345 if (env->exception_index >= EXCP_INTERRUPT) { 346 /* exit request from the cpu execution loop */ 347 ret = env->exception_index; 348 break; 349 } else if (env->user_mode_only) { 350 /* if user mode only, we simulate a fake exception 351 which will be handled outside the cpu execution 352 loop */ 353 #if defined(TARGET_I386) 354 do_interrupt_user(env->exception_index, 355 env->exception_is_int, 356 env->error_code, 357 env->exception_next_eip); 358 #endif 359 ret = env->exception_index; 360 break; 361 } else { 362 #if defined(TARGET_I386) 363 /* simulate a real cpu exception. On i386, it can 364 trigger new exceptions, but we do not handle 365 double or triple faults yet. */ 366 do_interrupt(env->exception_index, 367 env->exception_is_int, 368 env->error_code, 369 env->exception_next_eip, 0); 370 /* successfully delivered */ 371 env->old_exception = -1; 372 #elif defined(TARGET_PPC) 373 do_interrupt(env); 374 #elif defined(TARGET_MIPS) 375 do_interrupt(env); 376 #elif defined(TARGET_SPARC) 377 do_interrupt(env->exception_index); 378 #elif defined(TARGET_ARM) 379 do_interrupt(env); 380 #elif defined(TARGET_SH4) 381 do_interrupt(env); 382 #elif defined(TARGET_ALPHA) 383 do_interrupt(env); 384 #elif defined(TARGET_CRIS) 385 do_interrupt(env); 386 #elif defined(TARGET_M68K) 387 do_interrupt(0); 388 #endif 389 } 390 env->exception_index = -1; 391 } 392 #ifdef USE_KQEMU 393 if (kqemu_is_ok(env) && env->interrupt_request == 0) { 394 int ret; 395 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); 396 ret = kqemu_cpu_exec(env); 397 /* put eflags in CPU temporary format */ 398 CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 399 DF = 1 - (2 * ((env->eflags >> 10) & 1)); 400 CC_OP = CC_OP_EFLAGS; 401 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 402 if (ret == 1) { 403 /* exception */ 404 longjmp(env->jmp_env, 1); 405 } else if (ret == 2) { 406 /* softmmu execution needed */ 407 } else { 408 if (env->interrupt_request != 0) { 409 /* hardware interrupt will be executed just after */ 410 } else { 411 /* otherwise, we restart */ 412 longjmp(env->jmp_env, 1); 413 } 414 } 415 } 416 #endif 417 418 T0 = 0; /* force lookup of first TB */ 419 for(;;) { 420 SAVE_GLOBALS(); 421 interrupt_request = env->interrupt_request; 422 if (__builtin_expect(interrupt_request, 0) 423 #if defined(TARGET_I386) 424 && env->hflags & HF_GIF_MASK 425 #endif 426 ) { 427 if (interrupt_request & CPU_INTERRUPT_DEBUG) { 428 env->interrupt_request &= ~CPU_INTERRUPT_DEBUG; 429 env->exception_index = EXCP_DEBUG; 430 cpu_loop_exit(); 431 } 432 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ 433 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) 434 if (interrupt_request & CPU_INTERRUPT_HALT) { 435 env->interrupt_request &= ~CPU_INTERRUPT_HALT; 436 env->halted = 1; 437 env->exception_index = EXCP_HLT; 438 cpu_loop_exit(); 439 } 440 #endif 441 #if defined(TARGET_I386) 442 if ((interrupt_request & CPU_INTERRUPT_SMI) && 443 !(env->hflags & HF_SMM_MASK)) { 444 svm_check_intercept(SVM_EXIT_SMI); 445 env->interrupt_request &= ~CPU_INTERRUPT_SMI; 446 do_smm_enter(); 447 BREAK_CHAIN; 448 } else if ((interrupt_request & CPU_INTERRUPT_HARD) && 449 (env->eflags & IF_MASK || env->hflags & HF_HIF_MASK) && 450 !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 451 int intno; 452 svm_check_intercept(SVM_EXIT_INTR); 453 env->interrupt_request &= ~(CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ); 454 intno = cpu_get_pic_interrupt(env); 455 if (loglevel & CPU_LOG_TB_IN_ASM) { 456 fprintf(logfile, "Servicing hardware INT=0x%02x\n", intno); 457 } 458 do_interrupt(intno, 0, 0, 0, 1); 459 /* ensure that no TB jump will be modified as 460 the program flow was changed */ 461 BREAK_CHAIN; 462 #if !defined(CONFIG_USER_ONLY) 463 } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && 464 (env->eflags & IF_MASK) && !(env->hflags & HF_INHIBIT_IRQ_MASK)) { 465 int intno; 466 /* FIXME: this should respect TPR */ 467 env->interrupt_request &= ~CPU_INTERRUPT_VIRQ; 468 svm_check_intercept(SVM_EXIT_VINTR); 469 intno = ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_vector)); 470 if (loglevel & CPU_LOG_TB_IN_ASM) 471 fprintf(logfile, "Servicing virtual hardware INT=0x%02x\n", intno); 472 do_interrupt(intno, 0, 0, -1, 1); 473 stl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl), 474 ldl_phys(env->vm_vmcb + offsetof(struct vmcb, control.int_ctl)) & ~V_IRQ_MASK); 475 BREAK_CHAIN; 476 #endif 477 } 478 #elif defined(TARGET_PPC) 479 #if 0 480 if ((interrupt_request & CPU_INTERRUPT_RESET)) { 481 cpu_ppc_reset(env); 482 } 483 #endif 484 if (interrupt_request & CPU_INTERRUPT_HARD) { 485 ppc_hw_interrupt(env); 486 if (env->pending_interrupts == 0) 487 env->interrupt_request &= ~CPU_INTERRUPT_HARD; 488 BREAK_CHAIN; 489 } 490 #elif defined(TARGET_MIPS) 491 if ((interrupt_request & CPU_INTERRUPT_HARD) && 492 (env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && 493 (env->CP0_Status & (1 << CP0St_IE)) && 494 !(env->CP0_Status & (1 << CP0St_EXL)) && 495 !(env->CP0_Status & (1 << CP0St_ERL)) && 496 !(env->hflags & MIPS_HFLAG_DM)) { 497 /* Raise it */ 498 env->exception_index = EXCP_EXT_INTERRUPT; 499 env->error_code = 0; 500 do_interrupt(env); 501 BREAK_CHAIN; 502 } 503 #elif defined(TARGET_SPARC) 504 if ((interrupt_request & CPU_INTERRUPT_HARD) && 505 (env->psret != 0)) { 506 int pil = env->interrupt_index & 15; 507 int type = env->interrupt_index & 0xf0; 508 509 if (((type == TT_EXTINT) && 510 (pil == 15 || pil > env->psrpil)) || 511 type != TT_EXTINT) { 512 env->interrupt_request &= ~CPU_INTERRUPT_HARD; 513 do_interrupt(env->interrupt_index); 514 env->interrupt_index = 0; 515 #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) 516 cpu_check_irqs(env); 517 #endif 518 BREAK_CHAIN; 519 } 520 } else if (interrupt_request & CPU_INTERRUPT_TIMER) { 521 //do_interrupt(0, 0, 0, 0, 0); 522 env->interrupt_request &= ~CPU_INTERRUPT_TIMER; 523 } 524 #elif defined(TARGET_ARM) 525 if (interrupt_request & CPU_INTERRUPT_FIQ 526 && !(env->uncached_cpsr & CPSR_F)) { 527 env->exception_index = EXCP_FIQ; 528 do_interrupt(env); 529 BREAK_CHAIN; 530 } 531 /* ARMv7-M interrupt return works by loading a magic value 532 into the PC. On real hardware the load causes the 533 return to occur. The qemu implementation performs the 534 jump normally, then does the exception return when the 535 CPU tries to execute code at the magic address. 536 This will cause the magic PC value to be pushed to 537 the stack if an interrupt occured at the wrong time. 538 We avoid this by disabling interrupts when 539 pc contains a magic address. */ 540 if (interrupt_request & CPU_INTERRUPT_HARD 541 && ((IS_M(env) && env->regs[15] < 0xfffffff0) 542 || !(env->uncached_cpsr & CPSR_I))) { 543 env->exception_index = EXCP_IRQ; 544 do_interrupt(env); 545 BREAK_CHAIN; 546 } 547 #elif defined(TARGET_SH4) 548 if (interrupt_request & CPU_INTERRUPT_HARD) { 549 do_interrupt(env); 550 BREAK_CHAIN; 551 } 552 #elif defined(TARGET_ALPHA) 553 if (interrupt_request & CPU_INTERRUPT_HARD) { 554 do_interrupt(env); 555 BREAK_CHAIN; 556 } 557 #elif defined(TARGET_CRIS) 558 if (interrupt_request & CPU_INTERRUPT_HARD) { 559 do_interrupt(env); 560 env->interrupt_request &= ~CPU_INTERRUPT_HARD; 561 BREAK_CHAIN; 562 } 563 #elif defined(TARGET_M68K) 564 if (interrupt_request & CPU_INTERRUPT_HARD 565 && ((env->sr & SR_I) >> SR_I_SHIFT) 566 < env->pending_level) { 567 /* Real hardware gets the interrupt vector via an 568 IACK cycle at this point. Current emulated 569 hardware doesn't rely on this, so we 570 provide/save the vector when the interrupt is 571 first signalled. */ 572 env->exception_index = env->pending_vector; 573 do_interrupt(1); 574 BREAK_CHAIN; 575 } 576 #endif 577 /* Don't use the cached interupt_request value, 578 do_interrupt may have updated the EXITTB flag. */ 579 if (env->interrupt_request & CPU_INTERRUPT_EXITTB) { 580 env->interrupt_request &= ~CPU_INTERRUPT_EXITTB; 581 /* ensure that no TB jump will be modified as 582 the program flow was changed */ 583 BREAK_CHAIN; 584 } 585 if (interrupt_request & CPU_INTERRUPT_EXIT) { 586 env->interrupt_request &= ~CPU_INTERRUPT_EXIT; 587 env->exception_index = EXCP_INTERRUPT; 588 cpu_loop_exit(); 589 } 590 } 591 #ifdef DEBUG_EXEC 592 if ((loglevel & CPU_LOG_TB_CPU)) { 593 /* restore flags in standard format */ 594 regs_to_env(); 595 #if defined(TARGET_I386) 596 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); 597 cpu_dump_state(env, logfile, fprintf, X86_DUMP_CCOP); 598 env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); 599 #elif defined(TARGET_ARM) 600 cpu_dump_state(env, logfile, fprintf, 0); 601 #elif defined(TARGET_SPARC) 602 REGWPTR = env->regbase + (env->cwp * 16); 603 env->regwptr = REGWPTR; 604 cpu_dump_state(env, logfile, fprintf, 0); 605 #elif defined(TARGET_PPC) 606 cpu_dump_state(env, logfile, fprintf, 0); 607 #elif defined(TARGET_M68K) 608 cpu_m68k_flush_flags(env, env->cc_op); 609 env->cc_op = CC_OP_FLAGS; 610 env->sr = (env->sr & 0xffe0) 611 | env->cc_dest | (env->cc_x << 4); 612 cpu_dump_state(env, logfile, fprintf, 0); 613 #elif defined(TARGET_MIPS) 614 cpu_dump_state(env, logfile, fprintf, 0); 615 #elif defined(TARGET_SH4) 616 cpu_dump_state(env, logfile, fprintf, 0); 617 #elif defined(TARGET_ALPHA) 618 cpu_dump_state(env, logfile, fprintf, 0); 619 #elif defined(TARGET_CRIS) 620 cpu_dump_state(env, logfile, fprintf, 0); 621 #else 622 #error unsupported target CPU 623 #endif 624 } 625 #endif 626 tb = tb_find_fast(); 627 #ifdef DEBUG_EXEC 628 if ((loglevel & CPU_LOG_EXEC)) { 629 fprintf(logfile, "Trace 0x%08lx [" TARGET_FMT_lx "] %s\n", 630 (long)tb->tc_ptr, tb->pc, 631 lookup_symbol(tb->pc)); 632 } 633 #endif 634 RESTORE_GLOBALS(); 635 /* see if we can patch the calling TB. When the TB 636 spans two pages, we cannot safely do a direct 637 jump. */ 638 { 639 if (T0 != 0 && 640 #if USE_KQEMU 641 (env->kqemu_enabled != 2) && 642 #endif 643 tb->page_addr[1] == -1) { 644 spin_lock(&tb_lock); 645 tb_add_jump((TranslationBlock *)(long)(T0 & ~3), T0 & 3, tb); 646 spin_unlock(&tb_lock); 647 } 648 } 649 tc_ptr = tb->tc_ptr; 650 env->current_tb = tb; 651 /* execute the generated code */ 652 gen_func = (void *)tc_ptr; 653 #if defined(__sparc__) 654 __asm__ __volatile__("call %0\n\t" 655 "mov %%o7,%%i0" 656 : /* no outputs */ 657 : "r" (gen_func) 658 : "i0", "i1", "i2", "i3", "i4", "i5", 659 "o0", "o1", "o2", "o3", "o4", "o5", 660 "l0", "l1", "l2", "l3", "l4", "l5", 661 "l6", "l7"); 662 #elif defined(__arm__) 663 asm volatile ("mov pc, %0\n\t" 664 ".global exec_loop\n\t" 665 "exec_loop:\n\t" 666 : /* no outputs */ 667 : "r" (gen_func) 668 : "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14"); 669 #elif defined(__ia64) 670 struct fptr { 671 void *ip; 672 void *gp; 673 } fp; 674 675 fp.ip = tc_ptr; 676 fp.gp = code_gen_buffer + 2 * (1 << 20); 677 (*(void (*)(void)) &fp)(); 678 #else 679 gen_func(); 680 #endif 681 env->current_tb = NULL; 682 /* reset soft MMU for next block (it can currently 683 only be set by a memory fault) */ 684 #if defined(TARGET_I386) && !defined(CONFIG_SOFTMMU) 685 if (env->hflags & HF_SOFTMMU_MASK) { 686 env->hflags &= ~HF_SOFTMMU_MASK; 687 /* do not allow linking to another block */ 688 T0 = 0; 689 } 690 #endif 691 #if defined(USE_KQEMU) 692 #define MIN_CYCLE_BEFORE_SWITCH (100 * 1000) 693 if (kqemu_is_ok(env) && 694 (cpu_get_time_fast() - env->last_io_time) >= MIN_CYCLE_BEFORE_SWITCH) { 695 cpu_loop_exit(); 696 } 697 #endif 698 } /* for(;;) */ 699 } else { 700 env_to_regs(); 701 } 702 } /* for(;;) */ 703 704 705 #if defined(TARGET_I386) 706 /* restore flags in standard format */ 707 env->eflags = env->eflags | cc_table[CC_OP].compute_all() | (DF & DF_MASK); 708 #elif defined(TARGET_ARM) 709 /* XXX: Save/restore host fpu exception state?. */ 710 #elif defined(TARGET_SPARC) 711 #if defined(reg_REGWPTR) 712 REGWPTR = saved_regwptr; 713 #endif 714 #elif defined(TARGET_PPC) 715 #elif defined(TARGET_M68K) 716 cpu_m68k_flush_flags(env, env->cc_op); 717 env->cc_op = CC_OP_FLAGS; 718 env->sr = (env->sr & 0xffe0) 719 | env->cc_dest | (env->cc_x << 4); 720 #elif defined(TARGET_MIPS) 721 #elif defined(TARGET_SH4) 722 #elif defined(TARGET_ALPHA) 723 #elif defined(TARGET_CRIS) 724 /* XXXXX */ 725 #else 726 #error unsupported target CPU 727 #endif 728 729 /* restore global registers */ 730 RESTORE_GLOBALS(); 731 #include "hostregs_helper.h" 732 733 /* fail safe : never use cpu_single_env outside cpu_exec() */ 734 cpu_single_env = NULL; 735 return ret; 736 }
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