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2014-05-04

VLSIシンポジウムとIMW(International Memory Workshop)で5件の論文発表を行います。

6月のVLSIシンポジウムで2件、5月のIMW(International Memory Workshop)で3件の論文を発表します。

VLSIシンポジウムは、VLSI Circuits、VLSI Technologyが一件ずつです。VLSI Technologyで発表するのは、大学に移ってから初めてのこと。

プレスリリースも予定しています。

1.Shuhei Tanakamaru, Yuta Kitamura, Senju Yamazaki, Tsukasa Tokutomi and Ken Takeuchi, “Application-Aware Solid-State Drives (SSDs) with Adaptive Coding,” IEEE Symp. on VLSI Circuits.

【Abstract】Application-aware solid-state drives (SSDs) with 2 adaptive coding schemes to improve reliability are presented. In NAND flash memory, a direct reliability trade-off exists between write/erase (W/E) cycle and data-retention (DR) time. Thus, SSDs can be used for applications that have long DR time and low W/E cycles, or short DR time with high W/E cycles. The n-out-of-8 level cell (nLC) scheme is proposed for low-cost, long-term, archive storage which is indispensable to preserve human digital data. nLC eliminates the memory states of the Triple-Level Cell (TLC) NAND flash memory from 8 to 7…4 levels. Universal asymmetric coding (UAC) is also proposed for cloud/security camera/enterprise storage environments which require high endurance but shorter DR time. Both nLC and UAC optimize coding based on the applications’ required W/E cycle and DR. Bit-error rates (BERs) are improved by 79% and 52% with nLC and UAC, respectively.

2.Sheyang Ning, Tomoko Ogura Iwasaki, Kazuya Shimomura, Koh Johguchi, Glen Rosendale, Monte Manning, Darlene Viviani, Thomas Rueckes and Ken Takeuchi, “23% Faster Program and 40% Energy Reduction of Carbon Nanotube Non-volatile Memory with Over 10^11 Endurance,” IEEE Symp. on VLSI Technology.

【Abstract】Carbon nanotube (CNT) non-volatile memory provides excellent cell characteristics of >1011 endurance, low power, fast <5ns array program, and multi-level cell (MLC) potential. For the first time, optimal program methods are investigated considering speed, power and cell variability. Discrete cells are measured and a multiple-pulse reset scheme is proposed to reduce verify-reset time and a gate pulse verify-reset scheme further reduces array program energy by 40%.

3.Ayumi Soga, Chao Sun and Ken Takeuchi, “NAND Flash Aware Data Management System for High-Speed SSDs by Garbage Collection Overhead Suppression,” IEEE International Memory Workshop.

4.Tsukasa Tokutomi, Shuhei Tanakamaru, Tomoko Ogura Iwasaki and Ken Takeuchi, “Advanced Error Prediction LDPC for High-Speed Reliable TLC NAND-based SSDs,” IEEE International Memory Workshop.

5.Shuhei Tanakamaru, Shogo Hosaka, Koh Johguchi and Ken Takeuchi, “Performance and Reliability of NAND Flash/SCM Hybrid SSD during Write/Erase Cycling,” IEEE International Memory Workshop.

トラックバック - http://d.hatena.ne.jp/Takeuchi-Lab/20140504/1399152666
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