思い出しがてら
toplevel.v
`timescale 1ns / 1ps module toplevel( input CLK, ARDUINO_RESET, output LED0 ); pulse_generator generator(.CLK(CLK),.RST(ARDUINO_RST),.LED(LED0)); endmodule
pulse_generator.v
`timescale 1ns / 1ps module pulse_generator( input CLK,RST, output reg LED ); reg [25:0] cnt; wire en1hz = (cnt==26'd49_999_999_999); always @(posedge CLK) begin if(RST) cnt <= 26'b0; else if(en1hz) cnt <= 26'b0; else cnt <= cnt + 26'b1; end reg [3:0] sec; always @(posedge CLK) begin if(RST) sec <= 4'h0; else if (en1hz) if(sec==4'h9) begin sec <= 4'h0; LED <= ~LED; end else sec <= sec + 4'h1; end endmodule