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2010-02-16

Verilogブレゼンハム 01:51 Verilogでブレゼンハムを含むブックマーク

 プレゼンハムの直線描画アルゴリズムVerilogで書いた。

 signedを使う必要はないのだが、面倒なのでそのまま。モジュールにもなっていない物を貼って誰得なのか。リセットとか省略。1クロックごとにアドレス生成してFIFOに放り込むだけ。

reg signed [10:0]	linepatblt_x1;
reg signed [10:0]	linepatblt_y1;
reg signed [10:0]	linepatblt_x2;
reg signed [10:0]	linepatblt_y2;
reg signed [13:0]	lp_x;
reg signed [13:0]	lp_y;
wire signed [10:0]	lp_dx;
wire signed [10:0]	lp_dy;
wire signed [2:0]	lp_sx;
wire signed [2:0]	lp_sy;
reg signed [10:0]	lp_err;

assign lp_dx = (linepatblt_x2 > linepatblt_x1) ? (linepatblt_x2 - linepatblt_x1) : (linepatblt_x1 - linepatblt_x2);
assign lp_dy = (linepatblt_y2 > linepatblt_y1) ? (linepatblt_y2 - linepatblt_y1) : (linepatblt_y1 - linepatblt_y2);

assign lp_sx = (linepatblt_x2 > linepatblt_x1) ? 1 : -1;
assign lp_sy = (linepatblt_y2 > linepatblt_y1) ? 1 : -1;
always @ (posedge CLK or negedge RST_X)	begin
	if(RST_X)begin
		case(estat)
			0:	begin
				//カウンタセット
				ERRBIT <= 20;
				
				hcount <= 0;
				lp_x <= linepatblt_x1;
				lp_y <= linepatblt_y1;
				
				lp_fs <= 0;
				
				lp_err <= ( lp_dx >= lp_dy ) ? ( (lp_dy << 1) - lp_dx )  : ( (lp_dx << 1) - lp_dy);
				
				estat <= 1;
			end
			1:	begin
				//書き込み
				ERRBIT <= 21;
				if(BUF_COUNT < 200) begin
					
					BUF_WDATA <= {{3{1'b0}},lp_y[13:0] , lp_x[9:1] ,setcolor_A,setcolor_R,setcolor_G,setcolor_B,
										setcolor_A,setcolor_R,setcolor_G,setcolor_B};
					BUF_WRITE <= 1;
					if(lp_dx >= lp_dy) begin
						lp_x <= lp_x + lp_sx;
						lp_err <= ( lp_err+lp_dy+lp_dy >=0 ) ? ( lp_err +lp_dy + lp_dy - lp_dx - lp_dx) : ( lp_err + lp_dy + lp_dy );
						lp_y <= ( lp_err+lp_dy+lp_dy >=0 ) ? ( lp_y + lp_sy ) : ( lp_y );
						if(hcount == lp_dx) begin
							estat <= 2;
						end
					end else begin
						lp_y <= lp_y + lp_sy;
						lp_err <= ( lp_err+lp_dx+lp_dx >=0) ? ( lp_err +lp_dx + lp_dx -lp_dy - lp_dy ) : ( lp_err +lp_dx + lp_dx) ;
						lp_x <= ( lp_err+lp_dx+lp_dx >=0) ? ( lp_x + lp_sx ) : ( lp_x);
						if(hcount == lp_dy) begin
							estat <= 2;
						end
					end
					hcount <= hcount + 1;
					
				end else begin
					//FIFO待ち
					BUF_WRITE <= 0;
					BUF_WDATA <= 0;
				end
			end
			2:	begin
				ERRBIT <= 22;
				reg_read_wait <= 0;
				BUF_WRITE <= 0;
				BUF_WDATA <= 0;
			end
			
			default: begin
				
			end
		endcase
	end
end
トラックバック - http://d.hatena.ne.jp/xabre/20100216/1266339081